This invention relates generally to data processing mechanisms and more particularly to a serial-to-parallel interface capable of accepting multiple format types and operating in multiple modes.
Serial to parallel converters are used in a wide variety of circuit implementations to convert streams of serial data into sets of parallel data. Once converted, the parallel data can be stored into memory, or processed by digital data processing mechanisms, such as microprocessors.
The process of converting serial data into parallel data is a relatively straightforward one. The conversion is typically achieved by storing the serial data a bit at a time into a shift register, and then when the shift register is full, outputting all of the stored bits simultaneously to provide a set of parallel data. While the conversion process itself is straightforward, the design of a serial to parallel converter can be fairly difficult. This difficulty stems largely from the fact that the input to a serial to parallel converter can be from many different sources having many different formats, with each source and format possibly having its own set of preferences and requirements. For example, some data sources may require the serial to parallel converter to operate in slave mode such that the converter receives its clock signals from the data source, while other data sources may require the converter to operate in master mode such that the converter provides the clock signals to the data source. Also, some formats may send the serial data in a left justified fashion such that the valid data starts at the beginning of a data cycle, while other formats may send the serial data in a right justified fashion such that the valid data begins appearing in the middle of a data cycle. Because of these and other possible variations in data sources and data formats, it is difficult to design a general purpose serial to parallel converter that will work with all input sources and formats.
Several approaches have been taken to address the data source and data format variation problem. One approach is to implement a separate serial to parallel converter for each possible variation. Another approach is to implement complex combinational logic to take into account all possible variations. Both of these approaches suffer from significant drawbacks. These drawbacks include inflexibility (whenever a source or format is altered or added, the implementation of the converter needs to be altered) and impracticability (these approaches require too much chip space to be practically implemented). With such significant drawbacks, neither of these approaches provides a satisfactory solution. Hence, an improved serial to parallel converting mechanism is needed.
The present invention provides a versatile serial to parallel interface capable of both receiving multiple types of input formats and operating in multiple operational modes. According to one embodiment, the serial to parallel interface of the present invention comprises a multiplexer, a signal generator, and a register. The multiplexer receives serial data from at least one of a plurality of possible data sources and, in response to a set of selection signals, outputs one of the sets of serial data to the signal generator. The signal generator thereafter forwards the serial data to the register for storage.
In addition to forwarding the serial data to the register, the signal generator also generates clock and control signals. These signals are used to control the operation of the register to ensure proper serial to parallel conversion of the input serial data. In addition, these signals may also be provided to the source of the serial data to control the actions of the data source. In accordance with the present invention, the signal generator generates the clock and control signals in response to indication information provided to the signal generator. In one embodiment, this indication information includes information relating to: (1) the desired mode of operation (e.g. slave or master) of the serial to parallel interface; and (2) the format (e.g. left justified or right justified) of the incoming serial data. This indication information gives the signal generator all of the information that it needs regarding the data source and the incoming data. Armed with this information, the signal generator can generate all of the necessary signals for ensuring the proper operation of the serial to parallel interface.
According to one embodiment, the indication information is provided to the signal generator by way of an indication register. The contents of the indication register may be established by an external component, such as a microprocessor. Since the contents of the indication register determine the behavior of the signal generator, and since the contents of the indication register may be set by an external component, the indication register in effect provides a mechanism for enabling an external component to dictate the behavior of the signal generator. By enabling an external component to dictate the signal generator""s behavior, the present invention greatly simplifies the logic that needs to be implemented by the signal generator. Since the signal generator may be told what it needs to do, it need not implement complex logic to determine how it should be behave. Thus, the present invention provides the best of both worlds. Namely, it accommodates multiple input types and multiple operational modes without requiring complex circuitry. Hence, the present invention represents a significant improvement over the prior art.